ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
(10) Input/output discrete, lamp dimmer control,
frames, during three of which no synchro or resolver
and on/off control.
conversions are made, the entire sequence repeats itself.
The A/D converter is contained on the A/D converter
(a) Input discretes. The following inputs are
circuit card assembly.
received and made available for program access: IMU
ready, accelerometer coarse heater on, gyro coarse
(8) Platform input/output logic. The platform 1/0
heater on, gyro float to temperature, and IMU spares
logic accumulates the AV pulses from the platform and
no. 1, 2, and 3. In addition, the IMU fail discrete is
received for processing but is not available to the
platform. The platform I/O logic is contained on the
software.
platform circuit card assembly.
(b) Output discretes. The following outputs are
(a) V accumulation. Three AV accumulation
processed by the computer from software for subse-
channels are provided. Each channel has an eight-bit,
quent transmission to other system elements: PS flag
up/down counter for the accumulation of velocity
set, CDU flag set, IMU flag set, computer flag set, reset
pulses. Accumulation is provided by strobing each
all flags, XY gyro fast slew, and Z gyro fast slew. A
channel at the 2.4-kHz quantizer clock rate into its
power-on-reset signal is also made available.
individual flip-flop, thereby providing a one-bit sample
for each channel. Synchronization to the basic CPU
(c) Lamp dimmer control. The lamp dimmer
clock is implemented to eliminate any hazardous logic
control is a four-bit non-linear digital/analog converter
condition before sampling. Special logic is implemented
whose outputs, under software control, are used to
to inhibit counters from toggling during a program
control the lamp voltage to the CDU. For each of ten
input command of any accumulated velocity data. The
binary codes, a unique analog voltage is generated.
leading edge of the quantizer clock initiates the one-bit
(d) On/off control. Computer tumon occurs
accumulation process. The contents of the AV counters
when + 24V input power is applied. Power turnoff
are read under software control.
control has three modes of operation. Each of these
modes generates an off command to the power supply
(b) Gyro torguing. The platform I/O provides
and a power off interrupt to the CDU. An overtempera-
three channels of gyro torquing pulses. Each gyro chan-
ture condition in the computer will generate an off
nel has its own eight-bit up/down counter and is indi-
command. The software is also capable of generating an
vidually loaded with torque data under software control
off command. Normal shutdown occurs when the on/
and then is either increased or decreased at gyro torque
off input is activated and is followed by an enter
rate, providing full rate torquing. Periodic update under
command.
software control updates each counter.
e. Computer Power Supply. The computer power
(9) Serial data bus. The SDB functions as a bidi-
supply receives unregulated + 24V from the power
rectional communications link between the computer
supply and generates + 5V, + 15V, and 15V for
and various external devices. The SDB consists of a data
computer operation. See figure 2-2 for a functional
envelope, address evelope, bidirectional data line, and a
block diagram of the computer power supply. In addi-
continuous 250-kHz clock. All serial communications
tion, the computer power supply supplies a variable
are completely under programmed I/O control. To
voltage for the CDU display lamps and necessary con-
initiate a serial transfer, an address word is transmitted
trol signals for the PS and computer. The computer
to all devices using an OUT 12 instruction. All address
power supply consists of the following major elements:
words contain a device code (bits 0-2), a transmit/
receive bit (bit 3), and a self-test bit (bit 4). The balance
+ 5V switching regulator
of the 16 bits in the address word are a unique function
O to + 5V switching regulator
of each device. Data is transmitted to a device using an
OUT 11. Data is transmitted from a device to the
+ 15V switching regulator
computer using an INP 11 to command a serial transfer
Dc-todc converter
into the I/O shift register. This INP 11 results in the
accumulator receiving the complement of the previ-
+ 15V precision supply
ously transmitted computer word and can be used as a
15V precision supply
short-loop self-test feature. A second INP 11 transfers
the contents of the shift register to the CPU. A mini-
Control and monitor section
mum delay of 84 microseconds is required between
(1) +5 V switching regulator. The + 5V switching
program commands to the serial I/O. A discrete bit
regulator is located on the 5V power supply circuit
may be read by the computer to determine the results
card assembly. The + 5V switching regulator develops
of a parity test on received words and the serial bus
+ 5V with input variations of +20 to + 30V and with
logic may be checked for its busy state. The serial data
load variations of 3 to 18 amps. In addition to the
bus logic is contained on the data buffer circuit card
filtered + 24V unregulated input power, the + 5V
assembly.
2-7
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