ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
thereby allowing complete relocatibility of the associ-
contents of the memory register are then presented to
ated subroutines. When an interrupt signal occurs,
the adder unit input through the B-switch along with no
other interrupts are logically inhibited or masked out.
input (zero) from the A-switch. The output of the adder
The interrupt control and masks are contained on the
unit, representing the operand is then strobed into the
I/O controller card assembly.
accumulator. For the case where a 32-bit transfer is
executed, two 16-bit operands are sequentially strobed
(a) Priority interrupt. A priority interrupt is
into the memory register. Upon completion of two
generated by the time-out counter and just prior to
memory cycles, a full 32-bit operand is loaded into the
power shutdown. The time-out counter will oveflow if
accumulator.
it is not reset at least once every 125 milliseconds, The
d Input/Output Section The I/O section provides
overflow will generate a priority interrupt. A priority
an interface between the CPU and memory and devices
interrupt is generated one millisecond prior to com-
external to the computer. The I/O section is contained
puter power shutdown to permit the software to save
on I/O controller card assembly, data buffer circuit
any required data.
card assembly, I/O discrete circuit card assembly, ana-
(b) Service interrupt. A service interrupt is gen-
log-to-digital (A/D) converter circuit card assembly,
erated when the real-time counter overflows.
and platform I/O circuit card assembly, and consists of
the following major elements:
(c) Internal interrupt. The internal interrupt is
generated by an overflow or divide fault condition and
Programmed input/output control
is associated with the status register. Bit position 0 of
DMA control
the status register identifies an overflow and bit 1 a
divide fault.
Interrupt control and masks
(4) Real-time counter. The real-time counter is a
Real-time counter
hardware counter loadable and readable by the CPU; it
Data bus buffer
aids the program in determining the time between
events. In addition the real-time counter has an over-
Time-out counter
flow function that is used to generate the service inter-
A/D converter
rupt. The real-time counter is contained on the I/O
controller card assembly.
Platform I/O logic
(5) Data bus buffer. The data bus buffer provides
Serial data bus
buffering of the data bus between the I/O section and
I/O discrete, lamp dimmer control, and on/off control
CPU. This buffering is required because of the loading
in excess of the drive capability provided by the CPU,
(1) Programmed input/output control. Program-
The data bus buffer is contained on the data buffer
ed I/O refers to the communication of information
circuit card assembly.
between the CPU and the various external devices and
is initiated by the operational program. Programmed
(6) Time-out counter. The time-out counter is a
I/O is performed by the execution of instructions which
four-bit counter which generates a priority interrupt
input to or output from the CPU accumulator. The
when it overflows. This counter is periodically reset by
four-bit device address field in these instructions enables
the software so that a software failure is indicated if an
direct communication with 16 devices. Address decod-
overflow does occur and the bit indicator is set.
ing and control signal generation for the external de-
vices is performed by the I/O controller card assembly.
(7) Analog-to-digital converter. All analog signals
are routed through the A/D converter before process-
(2) DMA control DMA control provides a trans-
ing by the CPU. The A/D converter converts analog
fer of data between the memory and an external device
signals from the I MU into digital signals for subsequent
with CPU involvement. In this mode of operation,
processing. The A/D converter generates its basic tim-
memory cycles are obtained from the CPU by the
ing reference from positive-going crossovers of the 400-
external device which generates the address for the
Hz reference. Each crossover initiates a timing frame in
memory location to be a accessed on a request-response
which all the DC-to-digital signals and one of the
basis. The computer contains logic for eight DMA
channels but only one is used. Channel two is used for
resolver signal is the first conversion within the frame
the A/D conversion.
and is then followed by all the dc signals. Conversion of
(3) Interrupt control and masks. The interrupt
the resolver or synchro signal occurs at the time frame
control and masks provide interface between the CPU
which compensates for the phase shift for that particu-
lar signal. In this manner, conversions occur at the
and I/O section for the three separately addressable and
independent hardware interrupts. These interrupt func-
signal peaks and quadrature effects are minimized. After
ions are priority, service, and internal. No dedicated
each signal is converted, a DMA cycle is initiated and
addresses in memory are required for these interrupts,
the converted value is stored into memory. After eight
2-6
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