ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
(2) Control section. The control section decodes
1. The program counter, one of the RAM
instructions and generates the necessary microcom-
registers, is a 16-bit register that holds the next instruc-
mands and timing to control data flow through the data
tion to be accessed into memory. As each instruction is
section. The control section is contained on no. 1, no, 2,
executed, the program counter contents are incre-
and no. 3 control circuit card assemblies and consists of
mented by one, thus providing the address of the next
the following major elements:
instruction. The program counter is also used as a
reference register for addressing operands into memory.
Instruction register
2. The seven 16-bit index registers, also
Control logic
RAM registers, are generally used as reference registers
Status register
for memory address operations.
Arithmetic counter
3. The RAM 16-bit extension accumulator is
an extension of the accumulator. During instructions
Clock generator
where the operand is 32 bits in length, the extension
Direct memory access (DMA) controls
accumulator register is linked with the accumulator to
provide a 32-bit accumulator. The extension accumula-
Bus and switch controls
tor always contains the 16 least significant bits of data
(a) Instruction register. The 16-bit instruction
in double-precision operations.
register no. 1 control circuit card assembly receives the
4. The RAM 16-bit quotient register is used
instruction accessed from memory via the data bus. The
to hold the quotient (result) when the CPU executes a
output from the instruction register is routed to the
divide operation.
RAM controls and includes the instruction decode logic.
The RAM controls are used to address a RAM register
5. The RAM 16-bit base register is used
in accordance with the decoded instructions. The out-
primarily as a reference register for loading and storing
put from the instruction decode logic is used to control
the index registers.
the balance of the CPU.
6. Three RAM addresses are provided for
(b) Control logic. The control logic consists of
interrupts. These include external service requests (ser-
the state counter and state control logic. The state
vice interrupt address), internal error (internal interrupt
counter, located on no. 3 control circuit card assembly,
address), and power failure or program trace operations
is used primarily for execution of all CPU instructions.
(priority interrupt address). The contents of these three
As each state is entered, controls are set to enable
addresses can be modified.
portions of the instruction cycle to occur. The state
counter is controlled by the decode of the instruction to
(c) Memory register. The 16-bit memory regis-
be executed. Additional means for instruction execution
ter is used to receive information from memory via the
are provided by the state control logic. The logic and
SDB for execution during a CPU operation. The infor-
circuitry are located on no. 2 control circuit card
mation may be either a command or an operand.
assembly.
(d) Adder unit. The function of the adder unit is
(c) Status register. The 8-bit status register on
to operate logically on data under control of a CPU
no. 3 control circuit card assembly contains three indi-
instruction and to generate a result. The computation
cator bits and three interrupt bits. The remaining two
occurring in the adder unit results in an address modi-
bits are not used. The results of arithmetic computa-
fication or an execution of the instruction.
tions are used to set the condition indicators on the
status register. The occurrence of interrupts causes the
(e) A-switch. The A-switch controls flow of data
interrupt bits to be set. Output from the status register
into the adder unit from either the accumulator or the
is routed to the output switch.
random access memory.
(d) Arithmetic counter. The arithmetic counter
(f) B-switch. The B-switch controls data flow
located on no. 3 control circuit card assembly, is used
into the adder unit from the memory register, status
during execution of multioperation instructions such as
register, and arithmetic counter.
multiply, divide, shift and normalize operations.
(g) Output switch. The output switch feeds the
(e) Clock generator. The CPU operates with
adder unit output onto the data bus for memory ad-
synchronous control from a 4-MHz clock signal gener-
dressing, data storage, or input/output device commu-
ated on no. 3 control circuit card assembly,
nication.
(f) Direct memory access control Direct mem-
ory access (DMA) occurs when the CPU, I/O Section or
(h) Holding register. The 16-bit holding register
a test device needs to store data into memory or read
temporarily holds the adder unit outputs that are des-
data from memory. The DMA operation is controlled
tined for random access memory storage.
2-4
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