ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
data. The single card assembly memory consists of the
(h) Bus and switch controls. The bus and switch
following major elements:
controls provide the switching for the DMA and inter-
rupt control, The output of the bus and switch controls
Memory buffers
is routed to the output switch for switching onto the
Memory address register
SDB.
Memory
b. C o r e M e m o r y . The core memory contains the
timing and registers required for storing data in the
(1) Memory buffers. Separate input and output
core stack assembly. The data loop circuit card assem-
buffers are used, each 16 bits wide. The input buffer
bly, drive circuit card assembly, and core stack assembly
holds data at the memory during write cycles and the
output buffer drives memory data onto the data bus
make up the memory. The memory consists of t h e
following major elements:
during read cycles. A 16-bit operand or instruction
takes a single cycle while 32-bit operands require two.
Memory buffer register
(2) Memory address register. The memory address
Memory address register
register contains the address of the requested location in
memory. The address is latched at the beginning of a
Sense inhibit functions
cycle and held stable while the memory is being ac-
cessed. The location addressed can contain an instruc-
Core stack assembly
tion, operand or another address.
(1) Memory buffer register. The memory buffer
(3) Memory. The memory is partitioned in 48K
register is used to store the output of the memory
words of nonvolatile EEPROM and 16K words of static
during read operations and holds the input to memory
ram. The EEPROM retains program instructions and
storage during write operations. The memory buffer
constants when power is removed and can be updated
register is 16 bits to handle a 16-bit operand or instruc-
by the computer within the system. The ram provides a
tion. Two memory cycles are required for 32-bit oper-
read/write scratchpad for data.
ands.
c. Data Flow Orientation. A common bidirectional
data and address bus is used to establish orderly com-
(2) Memory address register. The memory address
munication between the memory CPU, I/O section, and
register contains the address of the requested location in
test devices. Each device on the bus is controlled by the
memory. The address may be an instruction address, an
CPU. Top priority is given to the I/O section in order
operand address, or an indirect address. The contents of
to enhance DMA. When the memory is in use, the CPU
the memory location addressed in turn may contain an
is still able to execute instructions which do not require
instruction, operand or another address.
continuous memory access, such as the multiply, shift
(3) Sense inhibit functions. Data storage and re-
and divide instructions.
trieval are accomplished by the inhibit drivers and sense
(1) Operation within the data section revolves
amplifiers. When data is to be accessed from an ad-
around use of a central adder unit. The inputs to the
dressed location, the contents of the selected location
adder unit are from the B-switch and the A-switch. The
are sensed via the sense inhibit wire and applied to the
output of the adder unit services all registers. In addi-
sense amplifiers. The sense amplifiers then feed the
tion, the adder unit also services the memory address
information into the memory buffer register. One
register and memory buffer register in the memory. For
group, of 16 bits, of the memory address register is then
the memory registers, the adder unit supplies both the
enabled and the data is sent to the CPU or input/
effective addresses and data to be stored on the same 16
output section via the SDB. When data is to be stored
lines of the output switch to the memory.
into an addressed location, the contents of the SDB
(from the CPU or I/O section) are strobed into the
(2) During an instruction fetch cycle, the instruc-
memory buffer register. The selected 16 bits of the
tion is received from the memory buffer register
memory address register are then fed to the inhibit
through the common bus and strobed into the instruc-
drivers and the data is written into the addressed loca-
tion register. In a memory reference instruction, the D
tion.
field modifies the address contained in the register
designated by the R field code, and the augmented
(4) Core stack assembly. The core stack assembly
address is sent to the memory address register via the
is organized in a conventional 3-wire coincident current
output switch for the operand fetch cycle.
manner with a storage capacity of 32,768 words. The
(3) Assuming that a single length load accumula-
memory word length is 16 bits.
tor instruction is in the instruction register, the operand
b.1 So/id State Memory. The solid state memory
fetch results in 16 bits of data being placed in the
contains the timing and registers required for storing
memory registers from the memory buffer register. The
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