ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
(g) Interrupt control The interrupt control
by no. 3 control circuit card assembly, and has priority
logic mechanizes three separately addressable indepen-
over normal instruction execution.
dent hardware interrupt functions. Three interrupt dis-
1. Memory input. To store information in
cretes, priority interrupt, service interrupt, and internal
the memory unit, the request ing device generates a
interrupt, cause the next instruction to be taken from
memory initiation request and the memory address
specifically related RAM address locations containing
input. The initiation request is sent to the CPU where
previously stored 16-bit addresses. The internal inter-
the CPU control logic determines access to the data
rupt aids the CPU to diagnose and interrupt operation
bus. When the request is accepted, the data to be stored
in the event of an arithmetic overflow or divide fault.
in memory is loaded on the SDB and stored in the
The service interrupt is normally associated with an
addressed memory location.
external device. The priority interrupt may be associ-
2. Memory output. To read information
ated with a power (failure) condition. For more infor-
from the memory unit, the requesting device generates
mation on the interrupts, refer to the 1/0 section
an initiation request and a memory address input in the
description.
same manner as for memory input transfer. When the
request is accepted, the data from the addressed mem-
ory location is loaded on the SDB and sent to the
requesting device.
2-4.1/(2-4.2 blank)
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